This is a continuation of my blog on design of a Camputers Lynx Z80 <-> ESP32 interface
You might want to start reading here first:
The short version:
Code is here:
The Long version:
At the top the lynx data bus is buffered by a bidirectional 245 , it's direction based on /RD
The next bit down is an (from the Z80's perspective) output port /58 used by the Lynx to control few extras on the FDC. This includes switching in and out the disk ROM overlay into the Lynx memory map. Bit 4 of /58 controls whether the ROM is enabled or not. I don't use this circuit any longer. The port is now emulated within the ESP with the rest.
Central to the schematic is the decode of 16 ports in the range 0x5x using a 139 and some OR gates. /IOREQ will drop and enable the 139. Bits 4 & 6 of the address bus must be High, Bit 5 must be Low (and is ORed in after the 139). The last OR gate I do not use now as it is not required to decode the A3 line on the hardware side.
The output (active LOW) of the decode circuit is then inverted to give a rising edge clock into the WAIT flip-flop.
This part of the circuit immediately drops the Z80 /WAIT line through an open collector stage (LS09).
/RESET is brought in so that on reset the FF is cleared properly.
A signal /CLEARWAIT comes from the ESP32 to clear the wait condition.
Voltage translation is (not) done by using 1K resistors and the forebearance of the ESP inputs until I get some new parts in.
The code is as tight as I could get it, I'm sure sprite_tm and BitLuni could show me a few gotchas / ways of speeding it up.
I'm waiting on a new ESP32 board with PSRAM which can hold the disk buffers, then WiFi might be possible.
And the Result:
LynxDOS loading the directory from the disk buffer
Loaded (and playing) Football Manager by Kevin Toms